rtl

Chisel: A Modern Hardware Design Language

翻译 - Chisel 3：现代硬件设计语言

Verilator open-source SystemVerilog simulator and lint system

翻译 - Verilator开源SystemVerilog模拟器和Lint系统

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

翻译 - 具有按序排列的内核，按序排列的内核，加速器等的敏捷RISC-V SoC设计框架

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷

Veryl: A Modern Hardware Description Language

Awesome Learning - Learn JavaScript and Front-End Fundamentals at your own pace

翻译 - 很棒的学习-以自己的节奏学习JavaScript和前端基础知识