rtl · GitHub Topics

#安卓#MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use L...

autolayout Android iOS uitableview uicollectionview constraints rtl grid-layout layout view CSS ui cocoapods Xcode

Objective-C 4.42 k

1 年前

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

翻译 - Chisel 3：现代硬件设计语言

chisel chisel3 Scala firrtl rtl chip-generator Verilog

Scala 4.19 k

21 小时前

chipsalliance / rocket-chip

Rocket Chip Generator

Scala rocket-chip chip-generator chisel RISC-V rtl

Scala 3.37 k

2 天前

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

翻译 - Verilator开源SystemVerilog模拟器和Lint系统

Verilog system-verilog verilog-simulator verilator compilers C++systemc rtl

C++ 2.76 k

1 天前

layoutBox / PinLayout

#IOS#Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

Swift layout-engine carthage cocoapod swift-library iOS layout rtl anchor ios-ui swift-framework language

Swift 2.39 k

10 个月前

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RISC-V rv32i Verilog fpga rtl core processor cpu

Verilog 2.23 k

5 天前

riscv-boom / riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

RISC-V boom chisel rtl rocket-chip Scala

Scala 1.84 k

5 天前

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opendb-database openroad lef Verilog timing-analysis def eda rtl gdsii C++tcl

Verilog 1.81 k

4 小时前

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

翻译 - 具有按序排列的内核，按序排列的内核，加速器等的敏捷RISC-V SoC设计框架

rocket-chip chip-generator chisel RISC-V rtl soc peripherals chipyard boom Rocket

Scala 1.78 k

1 天前

SpinalHDL / SpinalHDL

Scala based HDL

Scala rtl vhdl Verilog fpga

Scala 1.74 k

2 天前

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RISC-V vhdl fpga soc Microcontroller processor cpu system-on-chip embedded rtl rtos smp multi-core

VHDL 1.69 k

1 天前

MohammadYounes / rtlcss

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

ltr rtl CSS 国际化 (i18n)mirror flip right-to-left PostCSS

JavaScript 1.69 k

23 天前

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

asic magic yosys openroad skywater openram vlsi system-on-chip foundry rtl Verilog

Python 1.44 k

14 天前