asic

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

翻译 - 开源工艺设计套件，可用于SkyWater Technology Foundry的130nm节点。

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

SERV - The SErial RISC-V CPU

Haskell to VHDL/Verilog/SystemVerilog compiler

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

RISC-V CPU Core (RV32IM)

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

32-bit Superscalar RISC-V CPU

Modular hardware build system

Berkeley's Spatial Array Generator

RISC-V Cores, SoC platforms and SoCs

Digital Signature Service : creation, extension and validation of advanced electronic signatures

Various HDL (Verilog) IP Cores

VUnit is a unit testing framework for VHDL/SystemVerilog

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

#计算机科学# collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

A huge VHDL library for FPGA development

Code generation tool for control and status registers