verilator · GitHub Topics

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

翻译 - Verilator开源SystemVerilog模拟器和Lint系统

Verilog system-verilog verilog-simulator verilator compilers C++systemc rtl

C++ 2.76 k

1 天前

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

RISC-V cpu Verilog fpga verilator rv32im rv32i asic verification

Verilog 1.38 k

3 年前

ZipCPU / zipcpu

A small, light weight, RISC CPU soft core

fpga cross-compiler Verilog verilator cpu

Verilog 1.37 k

1 个月前

ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

RISC-V rv32i rv32im cpu fpga Verilog verilator asic branch-prediction Linux xilinx artix-7

Verilog 953

3 年前

chipsalliance / Cores-VeeR-EH1

VeeR EH1 core

processor risc RISC-V verilator open-source-hardware rtl fpga

SystemVerilog 857

2 年前

ultraembedded / cores

Various HDL (Verilog) IP Cores

Verilog rtl fpga verilator asic audio i2s spi uart usb

Verilog 749

4 年前

olofk / edalize

An abstraction library for interfacing EDA tools

eda fpga xilinx yosys synthesis Simulation Verilog vhdl systemverilog verilator

Python 668

5 天前

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Verilog verification synthesis fpga asic cdc verilator async

Verilog 311

10 个月前

mshr-h / vscode-verilog-hdl-support

HDL support for VS Code

Visual Studio Code systemverilog Verilog verilator ctags Hacktoberfest

TypeScript 310

5 天前

ZipCPU / wbuart32

A simple, basic, formally verified UART controller

fpga uart verilator Verilog serialport

Verilog 290

1 年前

tymonx / logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Verilog systemverilog systemc C++cmake verilator verification rtl Unit testing fpga asic xilinx

SystemVerilog 276

5 年前

chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core

verilator RISC-V processor open-source-hardware rtl fpga

SystemVerilog 266

5 天前

ZipCPU / sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

sd-card fpga Verilog verilator

Verilog 249

2 个月前

ZipCPU / dblclockfft

A configurable C++ generator of pipelined Verilog FFT cores

fft fpga Verilog verilator GNU General Public License

C++ 231

1 年前

ZipCPU / autofpga

A utility for Composing FPGA designs from Peripherals

fpga C++Verilog verilator

C++ 171

3 个月前

ZipCPU / vgasim

A Video display simulator

Verilog Video GNU General Public License fpga gtkmm verilator vga

Verilog 162

8 个月前

ZipCPU / openarty

An Open Source configuration of the Arty platform

fpga fpga-soc verilator

Verilog 126

1 年前

ZipCPU / dpll

A collection of phase locked loop (PLL) related projects

Verilog verilator fpga GNU General Public License

Verilog 103

1 年前

ZipCPU / wbscope

A wishbone controlled scope for FPGA's

fpga Verilog verilator debugging-tools

Verilog 77

1 年前

dpretet / svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Verilog systemverilog Test-driven development tdd-utilities Python simulator flow gtkwave foss testcase mit-license Simulation verilator

Python 74

5 个月前