risc · GitHub Topics

mortbopet / Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

risc RISC-V 教学 simulator Qt processor-architecture cpu-emulator computer-architecture

C++ 2.74 k

10 天前

LekKit / RVVM

The RISC-V Virtual Machine

RISC-V vm virtual-machine 模拟器 emulation C risc jit translation Linux

C 1.01 k

14 天前

chipsalliance / Cores-VeeR-EH1

VeeR EH1 core

processor risc RISC-V verilator open-source-hardware rtl fpga

SystemVerilog 857

2 年前

michaeljclark / rv8

RISC-V simulator for x86-64

isa simulator disassembler 模拟器 RISC-V binary-translation metadata histogram risc Linux

C++ 699

3 年前

andrescv / jupiter

RISC-V Assembler and Runtime Simulator

RISC-V simulator risc Assembly 教学 asm runtime

JavaScript 425

9 个月前

MIPT-ILab / mipt-mips

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

mips cpu cpu-cache branch-prediction computer-architecture simulator cpu-model risc Simulation optimizations RISC-V pipeline

C++ 347

3 年前

Wren6991 / RISCBoy

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

risc cpu pcb RISC-V Game Boy fpga

C 269

2 年前

kvakil / venus

RISC-V instruction set simulator built for education

risc 教学 RISC-V Assembly

Kotlin 194

3 年前

liuqdev / 8-bits-RISC-CPU-Verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

Verilog fsm risc cpu

Verilog 141

6 年前

Mariotti94 / WebRISC-V

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

risc RISC-V 教学 simulator processor-architecture computer-architecture PHP pipeline Assembly

PHP 137

1 年前

vmmc2 / Vulcan

RISC-V Instruction Set Simulator (Built for education).

RISC-V Assembly 教学 risc simulator computer-architecture

Dart 101

3 年前

nikolaydubina / go-hackers-delight

"Hacker's Delight" in Go

binary book C logic Assembly showcase risc bits

Go 99

22 天前

mrisc32 / mrisc32

MRSIC32 ISA documentation and development

cpu risc isa

TeX 90

2 年前

AluVM / aluvm

#区块链#AluVM: RISC functional machine base implementation

virtual-machine edge-computing 函数式编程 embedded-systems risc Microcontroller smart-contracts 区块链 Rust

Rust 62

10 天前

edson-acordi / 4bit-microcomputer

MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for education...

教学 Assembly 编程 cpu risc asm Open Source oshw computer logic-gates

Python 61

1 年前

openid / sharedsignals

OpenID Shared Signals Working Group Repository

risc

Makefile 60

12 天前

lxp32 / lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

fpga cpu risc vhdl Assembly

Assembly 60

3 个月前

fzipp / oberon

Project Oberon RISC emulator in Go

risc 模拟器 Go

Go 57

2 个月前

ben-marshall / croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

RISC-V Microcontroller cpu Verilog formal-verification risc yosys Cryptography crypto systemverilog verilator mit-license

SystemVerilog 44

3 年前

SuperJMN / Plotty

C language compiler from scratch for a custom architecture, with virtual machine and all

risc 模拟器 Universal Windows Platform Parser Parsing C#net 编译器 C virtual-machine

C# 43

3 年前