Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Haskell to VHDL/Verilog/SystemVerilog compiler
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
RISC-V Linux SoC, marchID: 0x2b
SystemVerilog compiler and language services
An abstraction library for interfacing EDA tools
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Functional verification project for the CORE-V family of RISC-V cores.
SystemVerilog parser library fully compliant with IEEE 1800-2017
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
80186 compatible SystemVerilog CPU core and FPGA reference design
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX