rv32i · GitHub Topics

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RISC-V rv32i Verilog fpga rtl core processor cpu

Verilog 2.23 k

5 天前

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

RISC-V cpu Verilog fpga verilator rv32im rv32i asic verification

Verilog 1.38 k

3 年前

sysprog21 / shecc

A self-hosting and educational C optimizing compiler

arm armv7 编译器自托管 C Linux RISC-V rv32i rv32im qemu cross-compiler elf

C 1.19 k

14 天前

ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

RISC-V rv32i rv32im cpu fpga Verilog verilator asic branch-prediction Linux xilinx artix-7

Verilog 953

3 年前

syntacore / scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

RISC-V rtl Verilog rv32i ip core

SystemVerilog 900

4 个月前

WangXuan95 / USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

RISC-V rv32i soc fpga rtl Verilog systemverilog cpu

SystemVerilog 388

1 年前

rafaelcalcada / riscv-steel

RISC-V 32-bit microcontroller developed in Verilog

RISC-V rv32i core uart cpu gpio Microcontroller processor spi system-on-chip

Verilog 168

17 天前

stnolting / riscv-gcc-prebuilt

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

gcc rv32i Linux RISC-V

Shell 98

18 天前

AngeloJacobo / RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

RISC-V Verilog rv32i cpu formal-verification

Verilog 80

1 年前

maikmerten / spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog

RISC-V fpga Verilog system-on-chip ice40 rv32i

C 68

3 年前

aignacio / nox

RISC-V Nox core

RISC-V rv32i

C 62

8 个月前

sysprog21 / rv32emu-legacy

RISC-V RV32I[MA] emulator with ELF support

RISC-V rv32i 模拟器 elf-parser

C 48

4 年前

panda5mt / KyogenRV

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

RISC-V rv32i fpga chisel3 chisel intel

Scala 44

4 年前

FelipeFFerreira / ITA-CORES

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

chip 框架 RISC-V rv32i asic

Verilog 44

1 年前

tscheipel / HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...

c-programming computer-architecture gtkwave pipelines processor-architecture RISC-V rv32i system-verilog systemverilog verilator

SystemVerilog 39

1 个月前

martinKindall / risc-v-single-cycle

A Single Cycle Risc-V 32 bit CPU

RISC-V rv32i systemverilog

SystemVerilog 38

2 年前

rob-ng15 / Silice-Playground

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

fpga forth RISC-V rv32i rv32im

C 35

2 年前

saursin / riscv-atom

An open-source 32-bit RISC-V soft-core processor

RISC-V processor cpu Microcontroller embedded fpga core soc rv32i system-on-chip Verilog

C++ 32

14 天前

calint / tang-nano-9k--riscv--cache-psram

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

rv32i systemverilog RISC-V

SystemVerilog 26

1 个月前

accomdemy / accomdemy_rv32i

伴伴學 RISC-V RV32I Architecture CPU

RISC-V rv32i

Verilog 26

2 年前