Open source ultrasound processing modules and building blocks
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
FPGA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit
Small Processing Unit 32: A compact RV32I CPU written in Verilog
Simple voltage glitcher implementation for the Lattice iCEstick Evaluation Kit
IP operations in verilog (simulation and implementation on ice40)
Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm