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xilinx-fpga

https://static.github-zh.com/github_avatars/f4pga?size=40

Documenting the Xilinx 7-series bit-stream format.

Python 829
3 个月前
https://static.github-zh.com/github_avatars/f4pga?size=40

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Jupyter Notebook 293
3 天前
https://static.github-zh.com/github_avatars/ultraembedded?size=40

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

Verilog 151
4 年前
https://static.github-zh.com/github_avatars/ingonyama-zk?size=40

blaze is a Rust library for ZK acceleration on Xilinx FPGAs.

Rust 144
1 年前
https://static.github-zh.com/github_avatars/triSYCL?size=40

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

C++ 120
10 个月前
https://static.github-zh.com/github_avatars/derekmulcahy?size=40

Xilinx Virtual Cable Server for Raspberry Pi

C 115
4 年前
https://static.github-zh.com/github_avatars/ultraembedded?size=40

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

C++ 93
5 年前
https://static.github-zh.com/github_avatars/chipsalliance?size=40

Plugins for Yosys developed as part of the F4PGA project.

Verilog 84
1 年前
https://static.github-zh.com/github_avatars/ultraembedded?size=40
Verilog 83
5 年前
https://static.github-zh.com/github_avatars/f4pga?size=40

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

SystemVerilog 81
4 年前
https://static.github-zh.com/github_avatars/f4pga?size=40
Shell 70
4 年前
https://static.github-zh.com/github_avatars/diogofferreira?size=40

💰 A simplified version of an FPGA bitcoin miner 💰

VHDL 53
6 年前
https://static.github-zh.com/github_avatars/fredrequin?size=40

Re-coded Xilinx primitives for Verilator use

Verilog 50
3 个月前
https://static.github-zh.com/github_avatars/ingonyama-zk?size=40

building blocks for accelerating ZK proofs over binary fields

Verilog 45
3 个月前
https://static.github-zh.com/github_avatars/stevenbell?size=40

Open-source CSI-2 receiver for Xilinx UltraScale parts

Verilog 37
6 年前
https://static.github-zh.com/github_avatars/sailordiary?size=40

中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

Verilog 32
8 年前
https://static.github-zh.com/github_avatars/KarenOk?size=40

Design and Implementation of a Simple-As-Possible 1 (SAP-1) Computer using an FPGA and VHDL.

VHDL 30
3 年前
https://static.github-zh.com/github_avatars/olivier-le-sage?size=40

Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.

VHDL 30
5 年前
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