Documenting the Xilinx 7-series bit-stream format.
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
blaze is a Rust library for ZK acceleration on Xilinx FPGAs.
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
Plugins for Yosys developed as part of the F4PGA project.
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
Re-coded Xilinx primitives for Verilator use
building blocks for accelerating ZK proofs over binary fields
中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.