Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Organization
Website
Wikipedia: 维基百科

chisel

@chipsalliance

Chisel: A Modern Hardware Design Language

翻译 - Chisel 3：现代硬件设计语言

chisel chisel3 scala firrtl rtl chip-generator verilog

Scala4.01 k

2 天前

verilator

@verilator

Verilator open-source SystemVerilog simulator and lint system

翻译 - Verilator开源SystemVerilog模拟器和Lint系统

verilog system-verilog verilog-simulator verilator compilers cpp systemc rtl

C++2.57 k

11 小时前

NyuziProcessor

Jeff Bush@jbush001

GPGPU microprocessor architecture

翻译 - GPGPU微处理器架构

fpga gpu-computing gpu verilog hardware microprocessor graphics processor-architecture

C2.01 k

15 天前

OpenROAD

@The-OpenROAD-Project

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opendb-database openroad lef verilog timing-analysis def eda rtl gdsii cpp

Verilog1.6 k

7 天前

MetroBoy

@aappleby

A repository of gate-level simulators and tools for the original Game Boy.

翻译 - MetroBoy-整个Game Boy的可播放的电路级仿真

verilog gameboy gameboy-emulator simulator emulator hdl

C++1.05 k

2 年前

USB_C_Industrial_Camera_FPGA_USB3

@circuitvalley

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

camera fpga usb usb3 verilog

Verilog879

1 年前