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集合主题趋势排行榜

#

Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Website
Wikipedia: 维基百科

logisim-evolution/logisim-evolution

logisim-evolution / logisim-evolution

Digital logic design tool and simulator

翻译 - 数字逻辑设计器和模拟器

logisim-evolution 教学 circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design fpga timing-diagram logisim vhdl Verilog

Java 5.46 k

9 天前

LeiWang1999 / FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga xilinx Verilog pynq

4.42 k

3 年前

chipsalliance/chisel

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

翻译 - Chisel 3：现代硬件设计语言

chisel chisel3 Scala firrtl rtl chip-generator Verilog

Scala 4.19 k

21 小时前

open-sdr/openwifi

open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

翻译 - 开源IEEE802.11 / Wi-Fi基带芯片/ FPGA设计

fpga ofdm 802-11 zynq Linux xilinx analog-devices mac80211 csma dma Verilog hls openwifi ad9361 sdr software-defined-radio ieee80211 wifi xilinx-fpga hardware

C 4.05 k

11 小时前

verilator/verilator

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

翻译 - Verilator开源SystemVerilog模拟器和Lint系统

Verilog system-verilog verilog-simulator verilator compilers C++systemc rtl

C++ 2.76 k

1 天前

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V soc cpu vhdl Verilog fpga

Assembly 2.69 k

1 个月前

SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

RISC-V cpu core china Verilog nuclei

Verilog 2.68 k

4 年前

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RISC-V rv32i Verilog fpga rtl core processor cpu

Verilog 2.23 k

5 天前

jbush001 / NyuziProcessor

GPGPU microprocessor architecture

翻译 - GPGPU微处理器架构

fpga gpu-computing gpu Verilog hardware microprocessor graphics processor-architecture

C 2.05 k

4 个月前

cocotb / cocotb

cocotb: Python-based chip (RTL) verification

Python vhdl Verilog verification Testing

Python 1.91 k

1 天前

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opendb-database openroad lef Verilog timing-analysis def eda rtl gdsii C++tcl

Verilog 1.81 k

4 小时前

FPGAwars/icestudio

FPGAwars / icestudio

#编辑器#❄️ Visual editor for open FPGA boards

editor fpga blocks Verilog ide JavaScript

JavaScript 1.75 k

5 天前

SpinalHDL / SpinalHDL

Scala based HDL

Scala rtl vhdl Verilog fpga

Scala 1.74 k

2 天前

pConst / basic_verilog

Must-have verilog systemverilog modules

fpga delay debounce encoder xilinx Verilog tcl synchronizer pwm uart hls

Verilog 1.73 k

4 个月前

amaranth-lang / amaranth

A modern hardware definition language and toolchain based on Python

翻译 - 更新的Python工具箱，用于构建复杂的数字硬件

Python 1.64 k

8 天前

analogdevicesinc / hdl

HDL libraries and projects

analog-devices Verilog fpga Hacktoberfest

Verilog 1.6 k

15 小时前

langhuihui / monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

翻译 - 媒体流服务器开发平台

livestream mediaserver hls WebRTC rtmp rtsp Verilog WebSocket flv rtp ts

JavaScript 1.58 k

1 天前

olofk/serv

SERV - The SErial RISC-V CPU

Verilog fpga asic RISC-V

Verilog 1.5 k

11 天前

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Haskell fpga vhdl Verilog systemverilog asic

Haskell 1.48 k

4 天前

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

asic magic yosys openroad skywater openram vlsi system-on-chip foundry rtl Verilog

Python 1.44 k

14 天前

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