chisel · GitHub Topics

OpenXiangShan / XiangShan

香山（XiangShan）是一款开源的高性能 RISC-V 处理器

RISC-V microarchitecture chisel

Scala 6.17 k

11 小时前

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

翻译 - Chisel 3：现代硬件设计语言

chisel chisel3 Scala firrtl rtl chip-generator Verilog

Scala 4.19 k

21 小时前

chipsalliance / rocket-chip

Rocket Chip Generator

Scala rocket-chip chip-generator chisel RISC-V rtl

Scala 3.37 k

2 天前

riscv-boom / riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

RISC-V boom chisel rtl rocket-chip Scala

Scala 1.84 k

5 天前

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

翻译 - 具有按序排列的内核，按序排列的内核，加速器等的敏捷RISC-V SoC设计框架

rocket-chip chip-generator chisel RISC-V rtl soc peripherals chipyard boom Rocket

Scala 1.78 k

1 天前

ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

chisel RISC-V rtl

Scala 564

7 个月前

RadicalCSG / Chisel.Prototype

Work in progress prototype for the Chisel Level Editor, for Unity

Constructive Solid Geometry mapping level-editor bsp chisel realtime Unity prototype

C# 496

5 个月前

m3rcer / Chisel-Strike

A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.

aggressor-scripts chisel cobalt-strike redteaming socks5

C# 447

1 年前

T-K-233 / RISC-V-Single-Cycle-CPU

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

logisim RISC-V chisel Verilog

Verilog 431

1 个月前

opiran-club / pf-tun

All-in-one OPIran scripts

chisel frp iptables optimizer socat ssh-tunnel tunneling

Shell 246

8 个月前

ucb-bar / chiseltest

The batteries-included testing and formal verification library for Chisel-based RTL designs.

Testing verification chisel

Scala 231

7 个月前

Azumi67 / Chisel_multipleServers

Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.

chisel openvpn reverse-tunnel tcp tunnel udp v2ray wireguard

Python 231

9 个月前

raster-gpu / raster-i

A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

fpga gpu chisel rasterizer

C++ 221

2 个月前