chipyard · GitHub Topics

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

翻译 - 具有按序排列的内核，按序排列的内核，加速器等的敏捷RISC-V SoC设计框架

rocket-chip chip-generator chisel RISC-V rtl soc peripherals chipyard boom Rocket

Scala 1.78 k

1 天前

firesim / FireMarshal

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

qemu distro workload Linux buildroot Fedora chipyard

Python 79

3 个月前

mit-ll / CEP

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

RISC-V Verilog fpga rocket-chip oshw soc chipyard

C 64

2 年前

MaxXSoft / Bossa

BOOM's Simulation Accelerator.

boom Rocket rocket-chip Simulation chipyard accelerator chisel RISC-V rtl soc verilator firrtl

Scala 13

3 年前

ThePituLegend / RISC-V_DE10-Nano

This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.

RISC-V fpga chipyard

Verilog 9

3 年前

RedFlag2017 / rocket-soc-tb

A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs

RISC-V chipyard soc

Verilog 9

5 年前

Fleker / chipyard-viewer

An online viewer for Chipyard output files

Hacktoberfest system-on-chip chipyard Web app

TypeScript 6

3 年前

yasnakateb / ChipyardIntegration

😱 RoCC Accelerator Integration with Chipyard

chipyard chisel chisel3 computer-architecture hardware hardware-acceleration Scala integration RISC-V Simulation verilator Rocket rocket-chip

4 个月前

slatte01 / ELEC-H505_Basic-RISC-V-in-order-core-accelerators-and-simple-SoC-generation-ChipYard-

This Github repository serves as a User Guide (UG) for new Chipyard users.

boom chipyard

Python 1

9 个月前

Kian75 / Chisel_Examples

chisel3 rtl chipyard fpga RISC-V

Scala 1

4 年前