vivado-hls

#计算机科学#Machine learning on FPGAs using HLS

DaCe - Data Centric Parallel Programming

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Recipe for FPGA cooking

翻译 - FPGA烹饪食谱

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

The second place winner for DAC-SDC 2020

Real-time binocular stereo vision FPGA system with OV5640 cameras

FPGA implementation of Canny edge detection by using Vivado HLS

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

FPGA acceleration of arbitrary precision floating point computations.

This project implements a convolution kernel based on vivado HLS on zcu104

A Vivado HLS Command Line Helper Tool

Lenet for MNIST handwritten digit recognition using Vivado hls tool

[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Real-time binocular stereo vision FPGA system with OV5640 cameras

Huffman encoding core (Vivado HLS Project)

MNIST accelerator using binary qunatization on Xilinx pynq-z2

Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.