The market for processors and microcontrollers is increasingly heated, and with the launch of the ISA (Instruction Set Achitecture) RISC-V, an open specification, it opens up a new opportunity for those who want to act either by researching or collaborating with new processors and microcontrollers.
Those who master the synthesis of Hardware with FPGA, can also propose more concretely new approaches for microcontrollers taking advantage of codes already written for the new architecture.
In this collection I try to present some renowned cores, and open the opportunity for other colleagues to collaborate with their suggestions.
PicoRV32 - A Size-Optimized RISC-V CPU
Spike, a RISC-V ISA Simulator
翻译 - Spike,RISC-V ISA模拟器
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
A very simple and easy to understand RISC-V core.
RSD: RISC-V Out-of-Order Superscalar Processor
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
QEMU with RISC-V (RV64G, RV32G) Emulation Support
A 32-bit RISC-V soft processor
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
A 32-bit Microcontroller featuring a RISC-V core
RiscyOO: RISC-V Out-of-Order Processor
A teaching-focused RISC-V CPU design used at UC Davis
Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compa...
basic example of litex on colorLight 5A-75B based on fpga_101/lab004
A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores
CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc