questasim · GitHub Topics

suoto / hdl_checker

#编辑器#Repurposing existing HDL tools to help writing better code

vhdl xilinx Verilog systemverilog Python syntax-checker lsp-server Vim language-server questasim

Python 201

9 个月前

Paebbels / JSON-for-VHDL

A JSON library implemented in VHDL.

vhdl JSON Parser fpga xilinx questasim Simulation synthesis

VHDL 77

3 年前

MJoergen / HyperRAM

Portable HyperRAM controller

xilinx artix fpga vhdl intel questasim

VHDL 54

3 个月前

wyvernSemi / mem_model

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Verilog Simulation questasim verilator vhdl

VHDL 22

4 个月前

Ghonimo / Pre_Silicon-AHB-to_APB-Verification

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

questasim Simulation systemverilog verification vip

SystemVerilog 22

1 年前

htminuslab / Modelsim-Unicorn

Modelsim QEMU Unicorn integration via the FLI

模拟器 questasim RISC-V vhdl

C 14

3 年前

NikLeberg / cosim_jtag

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

gdb vhdl questasim

C 10

6 个月前

MJoergen / Avalon

Utilities for Avalon Memory Map

fpga intel xilinx questasim memory

VHDL 9

8 个月前

Paebbels / pyIPCMI

A Python-based IP Core Management Infrastructure.

Python vhdl xilinx intel questasim synthesis Simulation infrastructure 数据库

Python 8

4 年前

dave2pi / SublimeLinter-contrib-vlog

SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog

sublimelinter questasim Verilog systemverilog

Python 7

7 年前

yuravg / eda-scripts

Collection of scripts for EDA tools

fpga questasim

Shell 6

4 个月前

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM...

questasim rtl rtl-design Verilog finite-state-machine synthesis systemverilog

Verilog 6

7 个月前

edaa-org / pyEDAA.ToolSetup

eda gtkwave Python questasim

Python 5

2 个月前

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modu...

systemverilog verification Verilog matrix-multiplication questasim

Verilog 5

9 个月前

yuravg / color_questasim

A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.

questasim

Perl 4

4 个月前

angrammenos97 / imc

In-Memory Accelerator Controller

controller edge-computing Verilog questasim RISC-V systemverilog

SystemVerilog 4

6 个月前

dave2pi / SublimeLinter-contrib-vcom

SublimeLinter plugin for linting VHDL with Modelsim vcom

sublimelinter questasim vhdl

Python 2

7 年前

kropotin4 / SystemVerilog-examples

Попытка написать несколько примеров кода на языке SystemVerilog.

questasim systemverilog rtl

SystemVerilog 2

4 年前

AlPrime2k1 / Finite-State-Machines

Latest addition to REPO : Folder with vending machine design and TB including code coverage report

code-coverage finite-state-machine questasim Verilog

HTML 2

2 年前

teekamkhandelwal / Uart_tx_main

Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional...

fpga questasim

Verilog 2

4 年前