openrisc · GitHub Topics

larsbrinkhoff / awesome-cpus

All CPU and MCU documentation in one place

翻译 - 所有CPU和MCU文档集中在一处

cpu avr openrisc Microcontroller vax xtensa microblaze datasheet sparc powerpc z80 arm Motorola 68000 RISC-V

HTML 1.91 k

2 年前

s-macke / jor1k

Online OR1K Emulator running Linux

模拟器 openrisc JavaScript Linux

JavaScript 1.75 k

3 年前

openrisc / mor1kx

mor1kx - an OpenRISC 1000 processor IP core

Verilog openrisc

Verilog 517

5 个月前

optimsoc / optimsoc

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

openrisc hardware

C 83

4 年前

gabriele-galeotti / SweetAda

Ada-language framework

arm avr embedded Motorola 68000 microblaze mips powerpc RISC-V sparc x86 x86-64 openrisc

Ada 39

18 天前

kuopinghsu / callgraph-gen

Generating the call graph from elf binary file

callgraph graphviz-dot RISC-V arm xtensa openrisc

Assembly 34

2 年前

PacoReinaCampo / MPSoC-DV

Multi-Processor System on Chip verified with UVM/OSVVM/FV

RISC-V openrisc formal-verification

SystemVerilog 28

2 个月前

PacoReinaCampo / SoC-DV

System on Chip verified with UVM/OSVVM/FV

RISC-V openrisc soc formal-verification

SystemVerilog 23

18 天前

ilyakurdyukov / ida-openrisc

OpenRISC 1000 processor module for IDA 7.x

ida idapython openrisc

Python 12

1 年前

janweinstock / or1kiss

An OpenRISC 1000 Instruction Set Simulator

openrisc simulator

C++ 10

2 年前

bandvig / or1k_marocchino

OpenRISC processor IP core based on Tomasulo algorithm

Verilog openrisc

Verilog 10

3 年前

PacoReinaCampo / PU-DV

Processing Unit verified with UVM/OSVVM/FV

RISC-V openrisc formal-verification

SystemVerilog 4

2 个月前

andrakis / Elispidae

Lisp-based stackless interpreter and platform, including microthreading. Features taken from Lisp and Erlang.

interpreter cplusplus-14 Visual Studio lambda makefile Linux openrisc x86-64

C++ 4

6 年前

PacoReinaCampo / MPSoC-OR1K

Multi-Processor System on Chip with OpenRISC-32 / OpenRISC-64

openrisc

SystemVerilog 2

2 个月前

PacoReinaCampo / PU-OR1K

Processing Unit with OpenRISC-32 / OpenRISC-64

openrisc

SystemVerilog 2

1 个月前

snps-virtualprototyping / ocx-or1kiss

OpenCpuX wrapper for the or1kiss OpenRISC ISS

openrisc

C++ 2

5 年前

seyang1 / pub-ips

systemverilog systemverilog-hdl Verilog asic RISC-V openrisc gpgpu gpgpu-computing gpu-computing processor processor-architecture

2 年前

PacoReinaCampo / SoC-OR1K

System on Chip with OpenRISC-32 / OpenRISC-64

openrisc simd soc

SystemVerilog 1

2 个月前

lucasasselli / or1200-onchip-obfuscator

This project is a modified verison of the OpenRISC 1200 open-source processor, designed to estimate the feasibility of using an On-Chip Software Obfuscator to reduce the controllability over software ...

openrisc

Verilog 1

4 年前

fusiled / ORPSocv3

openrisc Verilog

Assembly 0

8 年前