Yosys Open SYnthesis Suite
翻译 - Yosys开放合成套件
Learning FPGA, yosys, nextpnr, and RISC-V
翻译 - 学习FPGA，yosys，nextpnr和RISC-V
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Plugins for Yosys developed as part of the F4PGA project.
VHDL synthesis (based on ghdl)
Export netlists from Yosys to DigitalJS
Mutation Cover with Yosys (MCY)
User-friendly explanation of Yosys options
A collection of big designs to run post-synthesis simulations with yosys
SystemVerilog support for Yosys
Testing Ibex build using Yosys and open source toolchains.
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware us...
This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accele...