”yosys“ 的搜索结果

Yosys Open SYnthesis Suite

Learning FPGA, yosys, nextpnr, and RISC-V

SystemVerilog frontend for Yosys

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Plugins for Yosys developed as part of the F4PGA project.

VHDL synthesis (based on ghdl)

Export netlists from Yosys to DigitalJS

Mutation Cover with Yosys (MCY)

User-friendly explanation of Yosys options

SystemVerilog support for Yosys

A VHDL frontend for Yosys

Testing Ibex build using Yosys and open source toolchains.

A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware us...

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware us...

This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accele...