[WIP] Dockerize Synopsys/Cadence EDA tools
Synopsys Action consuming Synopsys scanning tools
This is now deprecated. Please see synopsys-detect.
Caffe models for use with Synopsys DesignWare EV6x Processors
Some useful documents of Synopsys
usb-device implementation for Synopsys USB OTG IP cores
Synopsys License patcher
Repository containing releases of prebuilt GNU toolchains for DesignWare ARC Processors from Synopsys (available from "releases" link below).
Synopsys Detect integration with Github Actions
SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
Scanning and analysis for Black Duck SCA products.
A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.