An open-source microcontroller system based on RISC-V
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
A build tool for PureScript projects
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP
翻译 - 由深度学习驱动的视觉导航引擎，可实现对口袋大小的四旋翼飞机的自主导航-在PULP上运行
pulp_soc is the core building component of PULP based SoCs
IP-XACT packaging of Pulpino by pulp-platform.org: https://github.com/pulp-platform/pulpino
RISC-V Debug Support for our PULP RISC-V Cores
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Common SystemVerilog components
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
Solves vehicle routing problem with Linear Programming using pulp package, which yields the optimal solution.
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
A 256-RISC-V-core system with low-latency access into shared L1 memory.
