Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de10-nano)
FPGA SoC code and application example for Hackaday Supercon 2019 badge
翻译 - Hackaday Supercon 2019徽章的FPGA SoC代码和应用示例
Hostmot2 FPGA code for SoC/FPGA platforms from Altera and Xilinx
FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
FPGA GPU design for DE1-SoC
Untethered (stand-alone) FPGA implementation of the lowRISC SoC
Tutorial for using the DE1-SoC/DE0-Nano-SoC boards for bare-metal and linux programming
SOC system using verilog on FPGA devices.
An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
DE10-Nano FPGA Configuration from Linux. Software to configure the FPGA portion of the Cyclone V SoC.
Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog
A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
development interface mil-std-1553b for system on chip
A 32bit RISC-V SoC on FPGA (EG4S20) that supports RT-Thread.
FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1
ADC sample using SG DMA of ZYNQ SoC FPGA (copy from ALINX example)
Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.
Useful resources for SOC Analyst and SOC Analyst candidates.
SOC Interview Questions
Espressif SoC serial bootloader utility
翻译 - ESP8266和ESP32串行Bootloader实用程序