”alveo-u200“ 的搜索结果

Vitis In-Depth Tutorials

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

Alveo U200 Slave Bridge with DDR4 Self Refresh

A simple tutorial to develop a CNN on an Alveo U200 card using Vitis AI

Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.

xilinx alveo u200 board

Datapath between host and FPGA(Alveo U200) via OpenCL and AXI channel. This is extracted from a larger project so there are some other files.

Vitis 2020.1 Acceleration Examples and Developed Large Size Matrix Multiplication Examples

This Repo contains a programs of calling Xilinx Alveo accelerator card from MATLAB

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

Run ethash opencl kernel on Xilinx's Alveo U50

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

翻译 - Vitis AI是Xilinx的开发堆栈，用于在Xilinx硬件平台（包括边缘设备和Alveo卡）上进行AI推理。

Custom YOLOv4 for apple recognition (clean/damaged) on Alveo U280 accelerator card using Vitis AI framework.